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Application Note 9862
Figure 3 shows a typical HIP6502BEVAL1 start-up into S3
sleep state while all outputs are enabled (MSEL = open,
EN5VDL = 1). The start-up sequence is similar to that of the
HIP6500BEVAL1 board, with the difference that the new
3.3V DUAL/SB output precedes all the other outputs, and the
3.3V MEM output replaces the 3.3V DUAL .
12VIN (2V/DIV)
5V DUAL
3.3V SB
5VSB
3.3V DUAL
2.5V CLK
2.5V MEM
5V DUAL
3.3V DUAL/SB
3.3V MEM
2.5V MEM
GND>
10ms/DIV
T0 T1 T2
FIGURE 4. HIP6500BEVAL1 START-UP IN ACTIVE STATE
(S0, S1) WITH ALL OUTPUTS ENABLED
2.5V CLK
GND>
T0T1
T2 T3
10ms/DIV
T4
Figure 5 shows the same start-up sequence into an active
state (S0, S1) on the HIP6502BEVAL1 evaluation board.
Except for the noted different output use and designator
FIGURE 3. HIP6502BEVAL1 START-UP IN SLEEP STATE
(S3) WITH ALL OUTPUTS ENABLED
Active-State Start-Up
Figure 4 also shows a start-up sequence, but this time into
an active state (S0, S1). As the enable pins only configure
the sleep state voltage support, this start-up sequence will
be the same, regardless of EN3VDL and EN5VDL status. In
Figure 4, SW1, SW2 and SW3 are all off and 5VSB is
applied to the HIP6500BEVAL1 board. Active state
differences, the start-up sequences of the boards are
extremely similar.
12VIN (2V/DIV)
5V DUAL
3.3V DUAL/SB
operation is enabled by switching on SW1, a few
milliseconds before T0. Invariably, the 3.3V SB output is
brought up shortly after 5VSB is applied to the IC, and it can
3.3V MEM
2.5V CLK
2.5V MEM
be seen present at the time the main ATX outputs are
coming up (T0). At time T0, the input voltages (3.3V, 5V,
12V) exceed the under-voltage thresholds (12V shown, only)
and the internal 25ms (typical) timer is initiated. Note the
GND>
10ms/DIV
typically poor regulation of the ATX supply resulting in a 10%
T0
T1
T2
overshoot at start-up (T0). Between T0 and T1, the
3.3V DUAL and 5V DUAL outputs undergo a quasi soft-start,
due to conduction through the body diodes of the active N-
MOS switches (Q4 and Q6). At time T1 the timer expires and
the two N-MOS transistors are turned on; simultaneously,
the 2.5V MEM and 2.5V CLK outputs begin a soft-start cycle,
reaching regulation limits at time T2.
4
FIGURE 5. HIP6502BEVAL1 START-UP IN ACTIVE STATE
(S0, S1) WITH ALL OUTPUTS ENABLED
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